National Institute Of Technology,Kurukshetra

DEPARTMENT OF SCHOOL OF VLSI DESIGN & EMBEDDED SYSTEM

Faculty

Name : Gaurav Saini
Designation : Assistant Professor
Qualification : Ph.D. (NIT Kurukshetra) M. Tech. (NIT Hamirpur)
Current Address :

Room No. 101, Deptt. of ECE NIT Kurukshetra Haryana, INDIA


Phone 1 (office) : 8950461132
Phone 2 (office) :
Email : gauravsaini@nitkkr.ac.in, gaurav.nitham@gmail.com

Area Of Intrest :

Students who would like to purse Ph.D. or any research-oriented work with me, are always welcome.

Microelectronics, Nanoscale VLSI Devices, Low Power VLSI Design

Experience :

  • Teaching and Research: 7.5 Years

Other :

Web Reference: Google Scholar

  1. List of publications:
  1. International Referred Journal:
  • Academic Year 2016-17
  1. G. Saini and S. Choudhary, "Investigation of trigate JLT with dual-k sidewall spacers for enhanced analog/RF FOMs," Journal of Computational Electronics (Springer), vol. 15, pp. 865-873, 2016. DOI: 10.1007/s10825-016-0866-6 (SCI listed)
  2. G. Saini and S. Choudhary, "Analog/RF performance of source-side only dual-k sidewall spacer trigate junctionless transistor with parametric variations," Superlattices and Microstructures (Elsevier), vol. 100, pp. 757-766, 2016. https://doi.org/10.1016/j.spmi.2016.10.037 (SCI listed)
  3. G. Saini and S. Choudhary, "Improving the performance of SRAMs using asymmetric junctionless accumulation mode (JAM) FinFETs," Microelectronics Journal (Elsevier), vol. 58, pp. 1-8, 2016. https://doi.org/10.1016/j.mejo.2016.10.004 (SCI listed)
  4. G. Saini and S. Choudhary, "Improving the subthreshold performance of junctionless transistor using spacer engineering," Microelectronics Journal (Elsevier), vol. 59, pp. 55-58, 2017. https://doi.org/10.1016/j.mejo.2016.11.012 (SCI listed)
  • Academic Year 2015-16
  1. G. Saini and S. Choudhary, "Asymmetric dual-k spacer trigate FinFET for enhanced analog/RF performance," Journal of Computational Electronics (Springer), vol. 15, pp. 84-93, 2016. DOI: 10.1007/s10825-015-0769-y (SCI listed)
  2. Swati Choudhary and Gaurav Saini, “A Hetero-Spacer-Dielectric Double-Gate Junctionless Transistor for Enhanced Analog Performance,” Int. Journal of Electrical & Electronics Engg. vol. 2, spl. issue 1, pp. 66-70, 2015.
  • Academic Year 2014-15
  1. Sudhanshu Choudhary, Gaurav Saini and S. Qureshi, "Impact of Radial Compression on the Conductance of Carbon Nanotube Field Effect Transistors," Modern Physics Letters B, (World Scientific Publication), vol. 28, no.2, pp. 1-9, 2014. DOI: http://dx.doi.org/10.1142/S0217984914500079 (SCI listed)
  • Before Academic Year 2014-15
  1. Gaurav Saini & Ashwani K Rana, “Physical Scaling Limits of FinFET Structure: A Simulation Study,” International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March 2011, pp. 26-35.

 

  1. International Conferences
  • Academic Year 2015-16
  1. M. Madhini and G. Saini, "Heterojunction tunnel FET with Heterodielectric BOX," International Conference on Communication and Signal Processing (ICCSP), Melmaruvathur, 2016, pp. 1743-1746.
  2. Rohit and Gaurav Saini, “A Stable and Power Efficient SRAM Cell,” IEEE International Conference on Computer Communication and Control (IC4­2015) organized by Medi-Caps Group of Institutions, Indore, M.P. India, pp. 117-121, 2015.
  3. Devendra Jakhar and Gaurav Saini, “Design of a novel regulated cascode current mirror,” IEEE International Conference on Computer Communication and Control (IC4-2015) organized by Medi-Caps Group of Institutions, Indore, M.P. India, pp. 438-441, 2015.
  • Before Academic Year 2014-15
  1. Bhargav, K.N.; Suresh, A.; Saini, Gaurav, "Stacked keeper with body bias: A new approach to reduce leakage power for low power VLSI design," Advanced Communication Control and Computing Technologies (ICACCCT), 2014 International Conference on , vol., no., pp.445,450, 8-10 May 2014.
  2. Dillep, P.; Saini, Gaurav, "Enhanced cascode node impedance to the improved recyclic folded cascode OTA," Advanced Communication Control and Computing Technologies (ICACCCT), 2014 International Conference on , vol., no., pp.451,455, 8-10 May 2014.
  3. Gaurav Saini, Ashwani K Rana, Pankaj K Pal & Sunil Jadav “Leakage Behavior of Underlap FinFET structure: A Simulation Study,” in ICCCT-2010, International Conference of Computer and Communication Technology, organized by MNNIT Allahabad & sponsored by IEEE on September 17-19,2010, pp. 302-305.
  4. Gaurav Saini, Ashwani K Rana & Manoj Kumar “SOI Versus FinFET Structure: A Comparative Simulation Study, in ICACC-2011, International Conference on Advances in Computing and Communication organized by NIT Hamirpur & sponsored by IEEE on April 8-10, 2011, pp. 351-353.
  5. Pankaj K Pal, Rituraj S Rathod, Ashwani K Rana & GauravSaini “New Low-Power Techniques: Leakage Feedback with Stack & Sleep Stack with Keeper,” in ICCCT-2010, International Conference of Computer and Communication Technology, organized by MNNIT Allahabad &sponsored by IEEE on September 17-19,2010, pp. 296-301.

 

  1. Academic/Administrative Contributions:
  • Timetable In-charge of School of VLSI Design and Embedded Systems since 2014-15.
  • Worked as Deputy Superintendent of Centre-5 during end semester examination May/June-2016.

 

  1. Seminars/conferences/STC/FDP/QIP etc. organized and participated

S. No.

Title

Venue

Period

Organized/ Participated

1.

Introduction to Analog and Digital VLSI Design

IIT Guwahati

10th to 14th April 2017

Participated

2.

Modeling, Simulation of Nano-Transistors

IIT Kanpur

13th to 17th February 2017

Participated

3.

SMDP-C2SD Cadence Tool Training Programme

PSG Coimbatore

23rd to 25th January 2017

Participated

4.

Modeling, Simulation and Characterization of Nano-Transistors

IIT Kanpur

26th to 30th October 2015

 

Participated

5.

Use of Process Design Kit (PDK) of Semiconductor Laboratory for designing VLSI circuits

School of VLSI Design and Embedded Systems, NIT Kurukshetra

July 31st and August 1st 2015

Organized

(Jointly)

6.

Nanoscale Science and Engineering: Materials, Electronics, Photonics, Biosensors and Beyond

IIT Indore

23th to 25th June 2014

Participated

7.

Developments in VLSI Devices and Technology (DiVDAT-13)

NIT Hamirpur

24th to 28th June 2013

Participated

 

  1. Projects and Thesis supervised and co-supervised within institute:

               M.Tech. : 13

               B.Tech. : 04