National Institute Of Technology,Kurukshetra

DEPARTMENT OF ELECTRONICS&COMMUNICATION ENGG.

Faculty

Name : Dr Ashutosh Nandi
Designation : Assistant Professor
Qualification : Phd (Microelectronics and VLSI) - IIT Roorkee M. Tech (VLSI Design) - NIT Hamirpur
Current Address :

DB-41, NIT Kurukshetra, Haryana, India - 136119


Phone 1 (office) : 7206227623, +917206227623, 01744-233 339
Phone 2 (office) :
Email : ashutosh.chl@gmail.com

Area Of Intrest :

  • Low power and low temperature VLSI design, device circuit co-design in digital/analog domain, device modeling of multigate semiconductor devices.
  • GATE qualified students who would like to purse Phd or any research-oriented work under me, are always welcome. I take PhD students from both ECE Dept. and School of VLSI. My updated profile can be accessed from google scholar.

Experience :

  • 2000 - 2008: Indian Navy (Group ‘B’ gazetted officer)
  • Sept. 2013 - till date: NIT Kurukshetra

Other :

Awards:

  • Full time MHRD sponsored research scholar at NIT Hamirpur and IIT Roorkee.
  • Commendation by Chief of Naval Staff on 04-12-2003.
  • Cash Award by The Flag Officer Commanding-in-Chief Southern Naval Command on 04-12-2005.

Approved Ongoing Projects:

Physics based accurate analytical modeling of AlGaN/GaN High electron mobility transistors

Sponsoring Agency: DRDO

Ph.D. Supervised:

1. Shubham Tayal "Analog Performance analysis of multigate MOSFETs" (Joined Jan 2016, Submitted June 2018)

PhD on Going:

  1. Shikhar Gupta "Device circuit co-design issues of Underlap FinFET" (Joined Jan 2016, Expected Submission June 2019)
  2. Manish Verma "Design and Modeling of AlGaN/GaN based HEMT" (Joined Oct. 2017, Expected Submission Dec. 2019)

M.Tech Dissertations:

MTech Completed:

  1. Neha Goel : Design and Analysis of FIR filters on xilinx platform
  2. Ashok kumar : Improved Analytical Modeling of DG MOSFET in Subthreshold Regime
  3. Rajan Verma : Verilog-A modelling of multigate MOSFETs
  4. Vikee : Analytical Modeling of Junctionless Transistor with Variable Separation Method
  5. Anubhuti Mittal : Comparative Analysis of 16-Order FIR Filters on Xilinx Platform
  6. Hardik Patel : Comparative Study of Error Tolerant Adders for High-Speed Low-Power Circuit
  7. Pruthvi Kosala : Analytical Fringe Capacitance Model of underlapped DG-MOSFET
  8. Ravi Sharma : TCAD Simulation Study of Ferroelectric DGFET
  9. Disha Yadav : Comparative Analysis of an IIR Filter on Xilinx Platform
  10. Avinash Kumar Singh : Design of Radix-2 FFT Structures on Xilinx Platform
  11. Mitashra Gupta: Comparative Study and Performance Analysis of High-K DGMOSFET based SRAM
  12. Pradeep Kumar Verma : Compact Modeling of the Effects of Parasitic Fringe Capacitance on Threshold Voltage of Underlap Double Gate MOSFET
  13. Karishma Malviya : Performance Analysis of FIR/IIR Filter on Xilinx Platform
  14. Saurabh Mittal : Monte Carlo Simulation of Multigate MOSFET
  15. Pallabi Biswas : Performance Analysis of Current Mode Amplifiers

Research Publications:

International Referred Journal:

IEEE- 06, Elsevier- 10, IET- 03, Others- 03

2018-19

  1. Ashutosh Nandi, N. Pandey and S. Dasgupta, “Analytical Modelling of Gate Stack DG-MOSFET in Subthreshold Regime by Green’s Function Approach,” Accepted in IEEE Transactions on Electron Devices 2018.
  2. N. Pandey, H-H Lin, Ashutosh Nandi and Y. Taur, "Modeling of Short-Channel Effects in DG MOSFETs: Green’s Function Method versus Scale Length Model," IEEE Transactions on Electron Devices, Vol. 65, no. 8, pp. 3112-3119, Aug. 2018.
  3. S. Tayal and Ashutosh Nandi, “Optimization of gate stack in junctionless Si-nanotube FET for analog/RF applications,” Elsevier Materials Science in Semiconductor Processing, vol. 80, pp. 63-67, June 2018.
  4. S. Tayal and Ashutosh Nandi, “Performance analysis of junctionless DG-MOSFET based 6T SRAM with gate-stack configuration,” IET Micro & Nano Letters, Vol. 13, No. 6, pp. 838-841, June 2018.
  5. S. Tayal and Ashutosh Nandi, “Enhancing the delay performance of junctionless Si nanotube based 6T SRAM,” Accepted in IET Micro & Nano Letters, June 2018.
  6. S. Tayal and Ashutosh Nandi, “Study of temperature effect on junctionless silicon nanotube FET concerning analog/RF performance,” Elsevier Cryogenics, Vol. 92, pp. 71-75, June 2018.

2017-18

  1. Ashutosh Nandi, N. Pandey and S. Dasgupta, “Analytical Modeling of DG-MOSFET in Subthreshold Regime by Green’s Function Approach,” IEEE Transactions on Electron Devices, Vol. 64, no. 8, pp. 3056-3062, Aug. 2017.
  2. Ashutosh Nandi and N. Pandey, “Accurate Analytical Modelling of Junctionless DG-MOSFET by Green’s Function Approach,” Elsevier Superlattices and Microstructures, Vol. 111, pp. 983-990, Nov. 2017.
  3. S. Tayal and Ashutosh Nandi, “Analog/RF performance Analysis of Inner Gate Engineered Junctionless Si Nanotube,” Elsevier Superlattices and Microstructures, Vol. 111, pp. 862-871, Nov. 2017.
  4. S. Gupta and  Ashutosh Nandi, “Effect of air spacer on analog performance of underlap tri-gate FinFET," Elsevier Superlattices and Microstructures, Vol. 109, pp. 693-701, Sept. 2017.
  5. S. Tayal and Ashutosh Nandi, “Study of 6T SRAM Cell using High-K Gate Dielectric based Junctionless Silicon Nanotube FET,” Elsevier Superlattices and Microstructures, Vol. 112, pp. 143-150, Dec. 2017. 
  6. S. Tayal and Ashutosh Nandi, “Analog/RF Performance analysis of channel engineered high-K gate stack based junctionless Trigate FinFET,” Elsevier Superlattices and Microstructures, Vol. 112, pp. 287-295, Dec. 2017. 
  7. S. Tayal and Ashutosh Nandi, “Effect of High-K Gate Dielectric In-conjunction with Channel Parameters on the Performance of FinFET based 6T SRAM,” in Journal of Nano-electronics and Optoelectronics, American Scientific Publishers, Vol. 13, No. 05, pp. 768-774, May 2018. 

2016-17

  1. Ashutosh Nandi, A. K. Saxena and S. Dasgupta, “Oxide Thickness and S/D Junction Depth Based Variation Aware OTA Design Using Underlap FinFET,” Elsevier Microelectronics Journal, Vol. 55, pp. 19-25, 2016.
  2. S. Tayal and Ashutosh Nandi, “Effect of FIBL in- conjuction with channel parameters on analog and RF FOM of FinFET,” Elsevier Superlattices and Microstructures, Vol. 105, pp. 152-162, 2017.
  3. A. Mittal, Ashutosh Nandi and D. Yadav, “Comparative study of 16-order FIR filter design using different multiplication techniques," IET Circuits, Devices & Systems, Vol. 11, No. 3, pp. 196-200, May 2017.

2014-2015

  1. Ashutosh Nandi, A. K. Saxena and S. Dasgupta, “Enhancing Low Temperature Analog Performance of Underlap FinFET at Scaled Gate Lengths,” IEEE Transactions on Electron Devices, Vol. 61, no. 11, pp. 3619-3624, Dec. 2014.
  2. N. Goel and Ashutosh Nandi, “Design of optimised FIR Filter using FCSD representation,” International Journal of Electrical and Electronics Engg., Vol. 2, no. 1, pp. 3-6, Apr. 2015.

Before 2014-15

  1. Ashutosh Nandi, A. K. Saxena and S. Dasgupta, “Design and analysis of Analog Performance of Dual-k Spacer Based Underlap N/P-FinFET at 12nm Gate Length,” IEEE Transactions on Electron Devices, Vol. 60, no. 5, pp. 1529-1535, May 2013.
  2. Ashutosh Nandi, A. K. Saxena and S. Dasgupta, “Analytical modelling of double gate MOSFET considering source/drain lateral gussian doping profile,” IEEE Transactions on Electron Devices, Vol. 60, no. 11, pp. 3705-3709, Nov. 2013.
  3. Ashutosh Nandi, A. K. saxena and S. Dasgupta, “Impact of Dual-k Spacer on Analog Performance of Underlap FinFET,” Elsevier Microelectronics Journal, Vol. 43, pp. 883-887, 2012.
  4. Ashutosh Nandi and R. Chandel, “Design and Analysis of Sub-DT Sub-domino Logics for Ultra Low Power applications,” Journal of Low Power Electronics, American Scientific Publishers, California, USA, Vol. 6 no. 4, pp. 513-520, 2010.
  1. A. K. Jaiswal, G. Saini , Ashutosh Nandi and K. Kant, “Robust Subthreshold Circuit Designing Using Sub-threshold Source Coupled Logic,” International Journal of Electronics Engineering, Vol. II, no.1, pp. 219-223, Jun. 2010.

International Conferences

2017-18

  1. D. Yadav and Ashutosh Nandi, “Comparative Analysis of Digital IIR Filter using Add and Shift Method on Xilinx Platform,” in IEEE International Conference on Control, Instrumentation, Communication and Computational Technologies, (ICCICCT-2016), 16-17 Dec. 2017.

2016-17

  1. M. Gupta and Ashutosh Nandi, “Impact of Matched High-K Gate Dielectric based DG-MOSFET on SRAM performance,” International Conference on Power, Control & Embedded Systems (ICPCES-2017) 19-20 May 2017.
  2. D. Yadav and Ashutosh Nandi, “Design of an IIR Filter using Vedic Multiplier with Carry Save Adder,” in IEEE International Conference on Recent Trends on Electronics Information Communication Technology, (ICCICCT-2016), 19-20 May 2017.
  3. M. Gupta and Ashutosh Nandi, “Enhancing The SRAM Performance of Gate Stacked DG-MOSFET,” IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology (RTEICT-2017) 19-20 May 2017.
  4. A. K. Singh and Ashutosh Nandi, “Design of Radix 2 Butterfly Structure using Vedic multiplier and CLA on Xilinx,” in IEEE Conference on Emerging Devices and Smart Systems (ICEDSS17), 04 Mar. 2017.
  5. A. K. Singh and Ashutosh Nandi, “Design of Four Point Radix-2 FFT Structure on Xilinx,” in International Conference on Intelligent Computing and Control (I2C2’17), 23-24 June 2017.
  6. P. Kumar and Ashutosh Nandi, “Effects of Parasitic Fringe Capacitance on Threshold Voltage of Underlap DG-MOSFET,” in IEEE Conference on Intelligent Computing and Control (I2C2’17), 23-24 June 2017.
  7. P. Kumar and Ashutosh Nandi, “Fringe Capacitance in Underlap DG-MOSFET,” in National Conference on Recent Advances in Mechanical Engineering, NIT Kurukshetra, 02-03 June 2017.

2015-16

  1. P. R. Kosala and Ashutosh Nandi, “Fringe Capacitance Model of a Double-Gate MOSFET with Gate Underlap,” IEEE Intl. Conf. on Recent Trends in Electronics, Information & Comm. Tech. (RTEICT), 2016.
  2. H. Patel and Ashutosh Nandi, “Modified Error Tolerant Adder for Digital Signal Processing Application,” IEEE Intl. Conf. on Micro-Electronics and Telecommunication Engineering (ICMETE-2016)", Ghaziabad, India, pp.293-295, Sept. 2016.
  3. R. Sharma and Ashutosh Nandi, “Subthreshold Slope Variations In Double Gate Ferroelectric FET Using Si:HfO­2 As Gate Oxide,” Intl. Conf. on Electrical, Electronics, computer science and Mathematics physical education and Management (ICEECMPE), July 2016. 
  4. R. Sharma and Ashutosh Nandi, “Study of Variations in Memory Window of Si:HfO2 based MFIS-FET,” Proceedings of International Conference on Micro-Electronics and Telecommunication Engineering (ICMETE), pp. 426-428, Sept. 2016. 
  5. A. Mittal and Ashutosh Nandi, “Design of 16-bit FIR Filter using Vedic Multiplier with Carry Save Adder,” Proceedings of 44th IRF International Conference, pp. 57-60, Nov. 2015.

2014-15

  1. N. Goel and Ashutosh Nandi, “Design of FIR Filter using FCSD Representation,” IEEE Intl. Conf. on Comp. Intel. and Comm. Tech. (CICT), pp. 617-620, Feb-2015. 
  2. R. Verma and Ashutosh Nandi, “Verilog-A modelling of DGMOSFET,” 3rd National Conference on Nanoscience and Instrumentation Technology (NCNIT-2015), NIT Kurukshetra, 06-07 June 2015.
  3. R Verma and Ashutosh Nandi, “Time delay estimation and modelling of DG MOSFET in Verilog-A environment,” 3rd National Conference on Nanoscience and Instrumentation Technology (NCNIT-2015), NIT Kurukshetra, 06-07 June 2015.
  4. A. K Sah and Ashutosh Nandi, “Improved analytical threshold voltage modelling of DG MOSFET,” 3rd National Conference on Nanoscience and Instrumentation Technology (NCNIT-2015), NIT Kurukshetra, 06-07 June 2015.

Before 2014-15

  1. Ashutosh Nandi, A. K. Saxena and S. Dasgupta, “Analog Performance analysis of Dual-k Spacer based Underlap FinFET,” in 16th International Symposium on VLSI Design and Test (VDAT 2012), Springer LNCS 7373, pp. 46-51, July 1-4, 2012.