Reversible logic Synthesis, Quantum-dot Cellular Automata (QCA), Fault Tolerant Architecture, Embedded System Design Applications, Low power VLSI design, Reconfigurable computing. Students who would like to pursue Ph.D. or any research-oriented work with me, are always welcome.
Experience :
Total experience:
Teaching & Research: 11 years
Guest Editor, Special Issue on “Recent Advances and Challenges in Quantum-Dot Cellular Automata”, Computers & Electrical
Engineering, Volume 102 September 2022, IF: 4.152.
Currently, editing a Book entitled “Quantum-Dot Cellular Automata Circuits for Nanocomputing Applications”, to be published
by CRC Press, Taylor & Francis Group.
Project submitted Under CRG scheme, Design and Synthesis of Quantum Cellular Automata Based Devices for Quantum Computing Applications, Dec 2021.
Others:List of publications:
Academic Year 2022-23
Jaiswal, V., Sasamal, T.N.: A Novel Approach to Design Multiplexer using Magnetic Quantum-Dot Cellular Automata. IEEE Embedded Systems Letters, 1 (2022).
https://doi.org/10.1109/LES.2022.3207193 SCI Indexed
Jaiswal, V., Sasamal, T.N.: Novel Approach for the Design of Efficient Full Adder in MQCA. The Journal of Supercomputing, (2022). https://doi.org/10.1007/s11227-022-04989-0 SCI Indexed
T. N. Sasamal, G. Saini and V. Jaiswal, “High Speed Comparator and Parity generator in QCA based on optimal XOR structure,” 2022 IEEE 7th Forum on Research and Technologies for Society and Industry Innovation (RTSI), 2022, pp. 13-18, doi: 10.1109/RTSI55261.2022.9905214.
Academic Year 2021-22
Academic Year 2019-20
Trailokya Nath Sasamal, Ashutosh Kumar Singh, Anand Mohan, “Optimal Realization of Full Adder in QCA using 5-input majority gate” submitted,” IEEE Sponsored International Conference on “Industry 4.0 Technology 2020” (I4Tech2020), 13-15, February 2020, VIT, Pune
Yethirajula, P.K., Sasamal, T.N., Parihar, D. (2021). Machine Learning Based Efficiency and Power Estimation of Circular Buffer. In: Sharma, R., Mishra, M., Nayak, J., Naik, B., Pelusi, D. (eds) Green Technology for Smart City and Society. Lecture Notes in Networks and Systems, vol 151. Springer, Singapore. https://doi.org/10.1007/978-981-15-8218-9_36
Kumar, S., Sasamal, T.N. (2021). Verilog Implementation of High-Speed Wallace Tree Multiplier. In: Sharma, R., Mishra, M., Nayak, J., Naik, B., Pelusi, D. (eds) Green Technology for Smart City and Society. Lecture Notes in Networks and Systems, vol 151. Springer, Singapore. https://doi.org/10.1007/978-981-15-8218-9_38
Book
Title: Quantum-Dot Cellular Automata Based Digital Logic Circuits: A Design Perspective, Trailokya Nath Sasamal, Ashutosh Kumar Singh, Anand Mohan
Studies in Computational Intelligence, Series Volume, 879, Springer 2020.
Book Chapters:
Gaur H.M., Sasamal T.N., Singh A.K., Mohan A., Pradhan D.K. (2020) Reversible Logic: An Introduction. In: Singh A., Fujita M., Mohan A. (eds) Design and Testing of Reversible Logic. Lecture Notes in Electrical Engineering, vol 577. Springer, Singapore
Gaur H.M., Sasamal T.N., Singh A.K., Mohan A. (2020) Fault Models and Test Approaches in Reversible Logic Circuits. In: Singh A., Fujita M., Mohan A. (eds) Design and Testing of Reversible Logic. Lecture Notes in Electrical Engineering, vol 577. Springer, Singapore
Sasamal T.N., Gaur H.M., Singh A.K., Mohan A. (2020) Novel Approaches for Designing Reversible Counters. In: Singh A., Fujita M., Mohan A. (eds) Design and Testing of Reversible Logic. Lecture Notes in Electrical Engineering, vol 577. Springer, Singapore
Sasamal T.N., Gaur H.M., Singh A.K., Mohan A. (2020) Reversible Circuit Synthesis Using Evolutionary Algorithms. In: Singh A., Fujita M., Mohan A. (eds) Design and Testing of Reversible Logic. Lecture Notes in Electrical Engineering, vol 577. Springer, Singapore
Academic Year 2018-19
International/National Conferences
Y. S. Chauhan and T. N. Sasamal, “Enhancing Security of AES Using Key Dependent Dynamic Sbox,” 2019 International Conference on Communication and Electronics Systems (ICCES), Coimbatore, India, 2019, pp. 468-473
Preeti prajapati, Trailokya nath sasamal. “Design of Digital to Analog Converter using Dual Pair Differential Amplifier in 180nm CMOS Technology”. Advances in Communication, Devices and Networking. Lecture Notes in Electrical Engineering. vol.537, PP.37- 44,2019,10.1007/978-981-13-3450-4_5
Academic Year 2017-18
Refereed Journals
Trailokya Nath Sasamal, Ashutosh Kumar Singh, Umesh Ghanekar, “Towards efficient design of reversible logic gates in QCA with power dissipation analysis,” International Journal of Theoretical Physics, Springer, Vol. 57, pp. 1167-1185, 2018. (SCI)
Trailokya Nath Sasamal, Ashutosh Kumar Singh, Umesh Ghanekar, “Design and implementation of D-Flip-op and RAM cell in majority logic-based quantum-dot cellular automata,” Journal of Circuits, Systems and Computers (World Scientific)(2018) https://doi.org/10.1142/S0218126619500798. (SCI)
Trailokya Nath Sasamal, Ashutosh Kumar Singh, Anand Mohan, “An efficient design of Quantum-dot Cellular Automata based 5-input majority gate with power analysis,” Microprocessors & Microsystems (2018), Elsevier, https://doi.org/10.1016/j.micpro.2018.03.002. (SCI)
Trailokya Nath Sasamal, Ashutosh Kumar Singh, Umesh Ghanekar, “Efficient Design of Coplanar Ripple Carry Adder in QCA,” IET Circuits, Devices & Systems(2018), DOI: 10.1049/iet- cds.2018.0020. (SCI)
Academic Year 2016-17
Refereed Journals
Trailokya Nath Sasamal, Ashutosh Kumar Singh, Umesh Ghanekar, “Design of non-restoring binary array divider in majority logic-based QCA,” Electronics Letters, vol. 52, pp. 2001-2003, 2016. (SCI)
Trailokya Nath Sasamal, Ashutosh Kumar Singh, Anand Mohan, “Efficient Design of Reversible logic ALU using Coplanar Quantum-dot Cellular Automata,” Journal of Circuits, Systems and Computers (World Scientific), Vol. 27, No. 2 (2018) 1850021. (SCI)
Ashvin Chudasama, Trailokya Nath Sasamal, Jyoti Yadav, “An Efficient Design of Vedic Multiplier using Ripple Carry Adder in Quantum dot-Cellular Automata,” Computers and Electrical Engineering Journal, Article reference CAEE2390. (Accepted) (SCI)
Book Chapters
Trailokya Nath Sasamal, Ashutosh Kumar Singh, Umesh Ghanekar, Design and analysis of ultra-low power QCA parity generator circuit,” In: Garg A., Bhoi A., Sanjeevikumar P., Kamani K. (eds) Advances in Power Systems and Energy Management. Lecture Notes in Electrical Engineering, Vol 436, pp 347-354, 2018. Springer, Singapore. (Scopus)
Trailokya Nath Sasamal, Ashutosh Kumar Singh, Umesh Ghanekar, Design of QCA-Based D Flip Flop and Memory Cell Using Rotated Majority Gate. In: Panigrahi B., Trivedi M., Mishra K., Tiwari S., Singh P. (eds) Smart Innovations in Communication and Computational Sciences. Advances in Intelligent Systems and Computing, vol 670, 2019, Springer, Singapore.
Trailokya Nath Sasamal, Ashutosh Kumar Singh, Umesh Ghanekar, “An efficient single layer crossing based 4-bit shift register using QCA,” In: Choudhary R., Mandal J., Bhattacharyya D. (eds) Advanced Computing and Communication Technologies. Advances in Intelligent Systems and Computing, Vol 562, pp. 315-325, 2018. Springer, Singapore. (Scopus)
International/National Conferences
Trailokya Nath Sasamal, Ashutosh Kumar Singh, Anand Mohan, “Design of Parity Preserving Combinational circuits using Reversible Gate,” In the proceeding of 2nd IEEE International Conference on Next Generation Computing Technologies (NGCT – 2016), University of Petroleum and Energy Studies, Dehradun,14-16 October 2016, pp. 631-638.
A. Kumar, Trailokya Nath Sasamal, “Design of Divider Using Taylor Series in QCA,” Energy Procedia Elsevier, vol. 117, pp. 818-825.
Namita, Trailokya Nath Sasamal, “Sequential Circuit Design Using Quantum-Dot Cellular Automata,” Energy Procedia Elsevier, vol. 117, pp. 442–449, 2017.
S. Rani, Trailokya Nath Sasamal, “A New Clocking Scheme for Quantum-dot Cellular Automata Based Designs with Single or Regular Cells,” Energy Procedia Elsevier, vol. 117, pp. 466-473, 2017.
Mohit Kumar, Trailokya Nath Sasamal, “An optimal design of 2-to-4 decoder in Quantum-dot Cellular Automata,” Energy Procedia, pp. 450-457, 2017.
Ramanand Jaiswal, Trailokya Nath Sasamal, “ Efficient Design of Exclusive-Or Gate using 5-Input Majority Gate in QCA,” Conf. Ser.: Mater. Sci. Eng. 225 012143.
A. Kumar, Trailokya Nath Sasamal, “Design of adder and binary multiplier in QCA using coplanar technique,” In International Conference on the Intelligent Computing and Control I2C2, 23-24 june 2017, Karpagam innovation center karpagam college of engineering coimbatore, India.
Mohit Kumar, Trailokya Nath Sasamal, “An architecture of Quantum-dot cellular ROM,” In International Conference on the Intelligent Computing and Control I2C2, 23-24 june 2017, Karpagam innovation center karpagam college of engineering coimbatore, India.
Ramanand Jaiswal, Trailokya Nath Sasamal, “Efficient Design of Full Adder and Subtractor using 5-input Majority gate in QCA,” Proceeding of IEEE Tenth International Conference on Contemporary Computing (IC3-2017), JIIT, Noida, Sept. 2017, India.
S. Rani, Trailokya Nath Sasamal, “Design of QCA circuits using new 1D clocking scheme,” In the proceeding of IEEE 2nd International Conference on Telecommunication and Networks TEL-NET 2017, Amity University Uttar Pradesh, Noida, India August 10-11, 2017.
Namita, Trailokya Nath Sasamal, “Design of 4-Bit Serial-Parallel Multiplier in Quantum-Dot Cellular Automata,” Proceeding of IEEE 4th International conference on Signal Processing, Computing and Control (ISPCC-2017), Jaypee University of Information Technology, Waknaghat, Sept. 2017, India.
Academic Year 2015-16
Refereed Journals
Trailokya Nath Sasamal, Ashutosh Kumar Singh, Anand Mohan, “Efficient design of reversible alu in quantum-dot cellular automata”, Optik, vol. 127, no. 15, pp. 6172-6182, 2016. (SCI)
Trailokya Nath Sasamal, Ashutosh Kumar Singh, Anand Mohan, ” An optimal design of Full adder based on 5-input majority gate in Coplanar Quantum-dot Cellular Automata “, Optik, vol. 127, no. 20, pp. 8576-8591, 2016. (SCI)
International/National Conferences
R. Kumawat, T. N. Sasamal, “Design of 1-bit and 4-bit Adder using Reversible Logic in Quantum-Dot Cellular Automata”, in Pros.of 2016 IEEE Int. Con. On Recent Trends in Electronics, Information & Communication Technology (RTEICT -2016), Sri Venkateshwara College of Engineering Bengaluru, pp. 606-610, May 2016.
R. Kumawat, T. N. Sasamal, “An Improved Design of 4-bit and 8-bit Ripple Carry Adder using Quantum-dot Cellular Automata”, in Pros.of 4th Int. Conf. on Advancements in Engineering & Technology (ICAET-2016), BGIET Sangrur (Punjab), pp. 219-223, March 2016.
S. P. S. Kushawaha, T. N. Sasamal, “Modified positive feedback adiabatic logic for ultra low power VLSI,” Computer, Communication and Control (IC4), 2015 International Conference on, Indore, 2015, pp. 1-5
Peeyush Sharma, Trailokya Nath Sasamal, “Minimization of Combinational Digital Circuit using Genetic Algorithm”, IEEE International Conference on Computational Intelligence and Computing Research (ICCIC-2015), VICKRAM COLLEGE OF ENGINEERING, Madurai, Tamilnadu, India, PP. 879-882, 10-12 dec 2015.
Yatin Gupta, Trailokya Nath Sasamal, “Implementation of Reversible Logic gates using Adiabatic Logic”, IEEE Power, Communication and Information Technology Conference(PCITC-2015), Siksha ‘O’ Anushandhan University, Bhubaneswar,India, 15-17 Oct 2015.
Naginder Singh, Trailokya Nath Sasamal, “Design and Synthesis of Goldschmidt Algorithm based Floating Point Divider on FPGA,” in International Conference on Communication and Signal Processing, pp. 1041-1044, 2016.
Naginder Singh, Trailokya Nath Sasamal, “Design and Synthesis of Single Precision Floating Point Division based on Newton-Raphson Algorithm on FPGA,” in MATEC Web of Conference, pp. 1-4, 2016.
Ashvin Chudasama, Trailokya Nath Sasamal, “Implementation of 4×4 Vedic Multiplier using Carry Save Adder in Quantum-Dot Cellular Automata,” In Proceedings of the 5th IEEE International Conference on Communication and Signal Processing-ICCSP’16, Adhiparasakthi Engineering College Melmaruvathur, Tamilnadu, India, 2016.
Academic Year 2014-15
Refereed Journals
Trailokya Nath Sasamal, Ashutosh Kumar Singh, and Anand Mohan, “Reversible Logic Circuit Synthesis and Optimization Using Adaptive Genetic Algorithm”, Procedia Computer Science, Elsevier, vol. 70, pp. 407-413, 2015 .(Scopus)
Trailokya Nath Sasamal, Ashutosh Kumar Singh, Anand Mohan, “Design of Two-Rail Checker Using a New Parity Preserving Reversible Logic Gate”, International Journal of Computer Theory and Engineering, vol. 7(4), pp. 311, 2015.
International/National Conferences
Shashank Singh, Trailokya Nath Sasamal,” Design of vedic multiplier using adiabatic logic”, IEEE International Conference on Futuristic Trends on Computational Analysis and Knowledge Management (ABLAZE) ,Amity university, Greater Noida, PP.438-441, 25-27 Feb. 2015
Gaurav Kumar, Trailokya Nath Sasamal,” Design and Analysis of Toffoli gate using Adiabatic”, International Conference on Computing, Communication & Automation (ICCCA) , Noida, PP. 1344 – 1348, 15-16 May 2015.
Mohan Kumar, Trailokya Nath Sasamal, “Design of FIR Filter Using PSO with CFA and Inertia Weight Approach”, IEEE International Conference on Computing, Communication & Automation (ICCCA), Noida, PP. 1331 – 1334, 15-16 May 2015.
Mohan Kumar, Trailokya Nath Sasamal, “Optimal Design of FIR filter using modified PSO approach”, International Conference on Advances in Electrical, Power Control, Electronics Engineering and Applied Communication Technology(EPEACT-2015), JNU New Delhi, 14-15 march 2015.
Short course on Modeling and Simulation of Nano-Transistors, IIT Workshops: kanpur, Feb. 13-17, 2017
Invited lectures/seminar, expert lectures delivered by the faculty, consultancy/sponsored projects:
Delivered training session entitled References and Citations in Latex in AICTE sponsored Short Term Training Program (STTP) on “Research Confront & Document Typesetting using LaTeX:202X” at ABES Institute of Technology Ghaziabad, Phase-I from Jan 11-16, 2021.
Delivered training session entitled References and Citations in Latex in AICTE sponsored Short Term Training Program (STTP) on “Research Confront & Document Typesetting using LaTeX:202X” at ABES Institute of Technology Ghaziabad, Phase-II from Jan 25-30, 2021.
Delivered training session entitled References and Citations in Latex in AICTE sponsored Short Term Training Program (STTP) on “Research Confront & Document Typesetting using LaTeX:202X” at ABES Institute of Technology Ghaziabad, Phase-III from Feb 22-27, 2021.
Delivered expert lecture entitled in AICTE Training And Learning (ATAL) Academy sponsored FDP on “Emergence of Reversible and Quantum Logic Circuits” ABES
Institute of Technology from 22/11/2021 to 26/11/2021
Honors and Awards:
Full-time MHRD sponsored research scholar at IIT BHU
Reviewer of the following journals:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Microprocessors and Microsystems – Elsevier
Defence Science Journal – DRDO
Computers and Electrical Engineering
International Journal of Circuit Theory and Applications
IET Circuits, Devices & Systems
Nano Communication Networks
Indian Journal of Pure & Applied Physics (IJPAP)
IETE Journal of Research
Frontiers of Information Technology & Electronic Engineering
Academic / Administrative Contributions at Department / Institute Level:
Hostel Warden (from 09 Nov 2018)
Faculty In-charge Hockey and Handball (2017-2019)
Faculty In-charge Athletics (2019-till date)
Prof. I/C Microbus Society (2014-till date)
Obsolescence, Labs research & Project Committee member (2017 -till date)
Coordinator and paper setter of various subjects in ECE Department NIT Kurukshetra (2013-2017)
Incharge Stock Verification, MBA department (2016)
Member of syllabus revision committees for UG and PG courses
Presiding Officer (2014), Micro Observer(2019) Election Commission of India
Seminars/conferences/STC/FDP/QIP etc. organized and participated:
Conference Secretary, International Conference IC4E2020, 6-7 Nov 2020, Springer AIS
Coordinator, ATAL Faculty Development Program 2-6 Aug 2021 on “Research Confront and Document Preparation Using Latex”, total grant Rs. 93,000/-
Coordinated Two days workshop on IOT and Ethical Hacking. Organized by Microbus society and supported by TEQIP.
Coordinating upcoming STC on “Image Processing and its Applications Using MATLAB” Deptt. of ECE, NIT Kurukshetra.
Short course on Modeling and Simulation of Nano-Transistors, IIT kanpur, Feb. 13-17, 2017
Digital Transformation in Teaching Learning Process (DTITLP) course organised by NPIU, and conducted by IIT Bombay on SWAYAM, March. 16-30, 2020
IIC Training program, 16th-17th January 2020, LPU, Phagwara-144411.
Projects and Thesis supervised and co-supervised within and outside institute: B.Tech./M.Tech./Ph.D.
Guided 25 M.Tech Thesis, 1 Ph.D student (registered in 2021)
