IC fabrication of 8-bit Vedic Multiplier using SCL 180nm Technology

The 8-bit Vedic Multiplier has been made on 180nm technology of Semi-Conductor Lab, Mohali. The Chip contains a total number of 40 pins arranged along a Quad Flat Package (QFP) with 10 pins on each side.

It has been shown that implementation of Vedic multiplication method results in

• Highly compact layout leading to small contribution of interconnections to the overall propagation delay. This is clearly indicated by relatively small difference between pre layout and post layout propagation delay as obtained by simulation.
• High speed. The speed of the proposed multiplier design has been shown to be significantly better than those reported earlier.
• Vedic multiplication method offers the advantage of design reuse in the sense that (n/2) x (n/2) multipliers and k- bit binary adders can be reused for design of (n x n) multiplier.

The use of Full adders having equal input to output delay results in glitch free output.

It has been shown that as the operand size increases the contribution of interconnects to the propagation delay increases. It also has been shown that implementation of Vedic multiplication method results in highly compact layout leading to small contribution of interconnections to the overall propagation delay. This is clearly indicated by relatively small difference between pre-layout propagation delay and post-layout propagation delay as obtained by simulation. This shows that optimized layout is of critical importance for the designing of fast multipliers.

IC fabrication of 8-bit level crossing ADC using SCL 180nm Technology

The 8-bit level crossing ADC has been made on 180nm technology of Semi-Conductor Lab, Mohali. The Chip contains a total number of 24 pins arranged along a dual in-line package (DIP) with 12 pins on both side.

LC-ADC gives 8-bit digital output for the magnitude of analog signal. It has a resolution of 8 mV (1 LSB). Input signal amplitude range is limited to 1.8 V. The total power consumed by LC-ADC varies from 80nW to 130nW as the slope of input signal varies from 0-4000 V/sec when parasitic capacitors and resistors are not taken into account. Reference voltages required are generated on chip using capacitor voltage divider.

An improved LC–ADC with low power consumption and small area along with reduced data size has been designed and implemented, and proposed for futuristic applications. The basic architecture is taken from literature and modified to achieve better performance characteristics. All the circuits and layouts have been designed in 180 nm CMOS technology [from SCL (Semi-Conductor Laboratory)] using cadence virtuoso analog design environment keeping supply voltage equal to 0.8V and simulations were performed using Hspice circuit simulator.The layout of LC-ADC has been given for fabrication but the chip has not been fabricated yet by the semiconductor laboratory. So, validation of the design could not be completed.

The outcome of the present research work is described as follows.

• The proposed LC–ADC givesoutput of 8- bits and has a resolution equal to 8mV with input voltage range of 0 – 1.8 V.
• Total power consumed by the proposed LC- ADC varies from 90nW to 184nW as the slope of input signal varies in range of 0-4000 V/sec. The maximum conversion time of LC–ADC is 0.34 µsec.
• The proposed LC–ADC is also tested by varying temperature from 0?C to 70?C. The simulation results exhibit that power consumption of LC–ADC varies exponentially with temperature (81.68nW to 228.24nW).
• The comparator designed in this work consumes 28nW- 30nW power at room temperature.

The low power dissipation and small area makes the proposed LC-ADC appropriate for bio medical applications and wireless communication devices.Future work will be dedicated on optimizing the performance parameters and implementation of the proposed design on latest technologies.