Designation:    Assistant Professor
Department:    Electronics & Communication Engg
Qualification:    Ph.D. (NIT Kurukshetra) M. Tech. (NIT Hamirpur)
Address:    

Room No. 123, Deptt. of ECE NIT Kurukshetra Haryana, INDIA

Publications:    

Papers published in the International Journals (SCI Listed) 

1. N. Yadav, S. Jadav, and G. Saini, “2-D Analytical Surface Potential Modeling and Simulation-Based Optimization of GoP-HD-DMDG-TFET for Enhanced Performance,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, doi: 10.1109/TCAD.2025.3649461.

2. Arashpreet Kaur, Sonia Saini, and Gaurav Saini, “Dual gate material H-channel vertical DGTFET: design, simulation and optimization study,”  Semiconductor Science and Technology, 40, 2025 125005. DOI 10.1088/1361-6641/ae17e7

3. Sonia Saini and Gaurav Saini, “Investigating the impact of dielectric modulation on multichannel junctionless Fin and nanosheet BioFET efficacy,” Physica Scripta, 100 (2025) 085014. https://doi.org/10.1088/1402-4896/adf266

4. Sonia Saini and Gaurav Saini, “Performance investigation of junctionless nanosheet FET with dual-k sidewall spacer using numerical simulations,” International Journal of Electronics, 113(2), 2025, 333–348. https://doi.org/10.1080/00207217.2025.2501295

5. Arashpreet Kaur, Devang Kailashkumar Vekariya, and Gaurav Saini, “Reversed C-shape Pocket Double Gate TFET with dual-κ Spacers,” Indian Journal of Pure & Applied Physics, Vol. 63, April 2025, pp. 312-318 DOI: 10.56042/ijpap.v63i4.16112

6. Nisha Yadav, Sunil Jadav, Gaurav Saini, “Linearity performance and harmonic distortion analysis of gate-over-pockets hetero-dielectric dual-metal-double-gate TFET for RF applications,” Micro and Nanostructures, Volume 199, 2025, 208074, ISSN 2773-0123, https://doi.org/10.1016/j.micrna.2025.208074.

7. Nisha Yadav, Sunil Jadav, Gaurav Saini, “Steep subthreshold swing Double-Gate tunnel FET using source pocket engineering: Design guidelines,” Micro and Nanostructures, Volume 195, 2024, 207951, ISSN 2773-0123, https://doi.org/10.1016/j.micrna.2024.207951.

8. Ganta Avinash and Gaurav Saini, “Improving On-state current and Ambipolarity of TFET using Gate-Drain and Gate Dielectric Engineering,” Indian Journal of Pure & Applied Physics, Vol. 62, July 2024, pp. 607-613 DOI: 10.56042/ijpap.v62i7.7715

9. Sonia Saini and Gaurav Saini, “Performance Comparison of Junctionless FinFET with Nanosheet FET and Device Design Guidelines,” Indian Journal of Pure & Applied Physics, Vol. 62, June 2024, pp. 490-502 DOI: 10.56042/ijpap.v62i6.7238

10. Arashpreet Kaur and Gaurav Saini, “Drain Source-Engineered Double-Gate Tunnel FET for Improved Performance,” Journal of Electronic Materials, Volume 53, pages 3901–3913, 2024 https://doi.org/10.1007/s11664-024-11109-6

11. Miriyala Durga Prasad and Gaurav Saini, “A Systematic Investigation of Dual Material Gate TFET for Improved Performance,” Indian Journal of Pure & Applied Physics Vol. 62, March 2024, pp. 229-237. DOI: 10.56042/ijpap.v62i3.5888

12. Arashpreet Kaur and Gaurav Saini, “Design and Analysis of a Novel Asymmetric Source Dual-Material DG-TFET with Germanium Pocket” Silicon 15, 2889–2900 (2023). https://doi.org/10.1007/s12633-022-02202-8

13. Nisha Yadav, Sunil Jadav, Gaurav Saini, “Impact of Gate Length and Doping Variation on the DC and Analog/RF Performance of sub-3 nm Stacked Si Gate-All-Around Nanosheet FET” Silicon 15, 217–228 (2023). https://doi.org/10.1007/s12633-022-01989-w

14. Nisha Yadav, Sunil Jadav, Gaurav Saini, “Geometrical Variability Impact on the Performance of Sub-3 nm Gate-All-Around Stacked Nanosheet FET” Silicon 14, 10681–10693 (2022). https://doi.org/10.1007/s12633-022-01770-z

15. Sujit Kumar Singh, Awnish Kumar Tripathi, Gaurav Saini, Study on the negative transconductance behaviour in GaAs/AlGaAs based HEMT, Superlattices and Microstructures, Volume 146, 2020, 106684, ISSN 0749-6036, https://doi.org/10.1016/j.spmi.2020.106684.

16. Muktasha Maji, Gaurav Saini, “Modeling of dual material surrounding split gate junctionless transistor as biosensor”, Superlattices and Microstructures, Volume 135, 2019, 106290, ISSN 0749-6036, https://doi.org/10.1016/j.spmi.2019.106290.

17. Abhinav Chauhan, Gaurav Saini, Pavan Kumar Yerur, “Improving the performance of dual-k spacer underlap Double Gate TFET, Superlattices and Microstructures, vol. 124, pp. 79-91, 2018.

18. G. Saini and S. Choudhary, “Asymmetric dual-k spacer trigate FinFET for enhanced analog/RF performance,” Journal of Computational Electronics (Springer), vol. 15, no. 1,  pp. 84-93, 2016.

19. G. Saini and S. Choudhary, “Investigation of trigate JLT with dual-k sidewall spacers for enhanced analog/RF FOMs,” Journal of Computational Electronics (Springer), vol. 15, no. 3, pp. 865-873, 2016.

20. G. Saini and S. Choudhary, “Analog/RF performance of source-side only dual-k sidewall spacer trigate junctionless transistor with parametric variations,” Superlattices and Microstructures (Elsevier), vol. 100, pp. 757-766, 2016.

21. G. Saini and S. Choudhary, “Improving the performance of SRAMs using asymmetric junctionless accumulation mode (JAM) FinFETs,” Microelectronics Journal (Elsevier), vol. 58, pp. 1-8, 2016. 

22. G. Saini and S. Choudhary, “Improving the subthreshold performance of junctionless transistor using spacer engineering,” Microelectronics Journal (Elsevier), vol. 59, pp. 55-58, 2017.

23. Sudhanshu Choudhary, Gaurav Saini and S. Qureshi, “Impact of Radial Compression on the Conductance of Carbon Nanotube Field Effect Transistors,” Modern Physics Letters B, (World Scientific Publication), vol. 28, no.2, pp. 1-9, 2014.

Paper published in International Journal (Non-SCI) 

1. Swati Choudhary and Gaurav Saini, “A Hetero-Spacer-Dielectric Double-Gate Junctionless Transistor for Enhanced Analog Performance,” Int. Journal of Electrical & Electronics Engg. vol. 2, spl. issue 1, pp. 66-70, (2015).
2. G. Saini and A. Rana, “Physical scaling limits of FinFET structure: A simulation study,”
   International Journal of VLSI design & Communication Systems (VLSICS), 2, 26-35, 0976-1527, 2010.

Papers published in International Conferences

1. Aryan Kumar, Gaurav Saini, “A Comparative Study of Deep Learning Approaches for Early Detection of Sugarcane Diseases,” Procedia Computer Science, volume 260, 2025, pages 182-190, ISSN 1877-0509, https://doi.org/10.1016/j.procs.2025.03.192
2. A. Rajyan and G. Saini, “SystemVerilog-Based Design of an RV32I Compliant RISC-V Processor Core,” 2024 5th IEEE Global Conference for Advancement in Technology (GCAT), Bangalore, India, 2024, pp. 1-5, doi: 10.1109/GCAT62922.2024.10923874.
3. Rajyan, Matin and G. Saini, “Comparative Study of Nanowire FET & Internal Gate Nanowire FET,” 2024 2nd International Conference on Device Intelligence, Computing and Communication Technologies (DICCT), Dehradun, India, 2024, pp. 1-5, doi: 10.1109/DICCT61038.2024.10532940.
4. Beniwal and G. Saini, “Enhancing the Performance of DG-TFET Using Si/Ge Source n+Pocket Engineering,” 2023 International Conference on System, Computation, Automation and Networking (ICSCAN), PUDUCHERRY, India, 2023, pp. 1-5, doi: 10.1109/ICSCAN58655.2023.10395777.
5. Yadav, S. Jadav and G. Saini, “A Review on Role of Epitaxial Engineering in Improving the Drive Current and Subthreshold Swing in Area Scaled Tunnel FETs,” 2023 International Conference on Computer, Electronics & Electrical Engineering & their Applications (IC2E3), Srinagar Garhwal, India, 2023, pp. 1-5, doi: 10.1109/IC2E357697.2023.10262458.
6. N. Sasamal, G. Saini and V. Jaiswal, “High-Speed Comparator and Parity generator in QCA based on optimal XOR structure,” 2022 IEEE 7th Forum on Research and Technologies for Society and Industry Innovation (RTSI), Paris, France, 2022, pp. 13-18, doi: 10.1109/RTSI55261.2022.9905214.
7. Yadav, S. Jadav and G. Saini, “DC and Analog/RF Performance Analysis of Multi-Bridge Channel FET with Variation in Gate Work Function,” 2022 International Conference for Advancement in Technology (ICONAT), 2022, pp. 1-4, doi: 10.1109/ICONAT53423.2022.9726102.
8. Ankit Kulshrestha, Sajal Samaiya, Onkar Nath Jha, Gaurav Saini, “Design of High Speed and Power Efficient 16 × 8 SRAM Memory Using Improved 4 × 16 Decoder,” Micro and Nanoelectronics Devices, Circuits and Systems: Proceedings of MNDCS 2021. doi.org/10.1007/978-981-16-3767-4_14.
9. Sujit Kumar Singh, Awnish Kumar Tripathi, Gaurav Saini, “Study on the Negative Transconductance in a GaN/AlGaN-Based HEMT,” Proceedings of the International Conference on Paradigms of Computing, Communication and Data Sciences: PCCDS 2020, 377-388, Springer Singapore, 2021.
10. Maji and G. Saini, “Performance Enhancement of Non-uniformly Doped Junctionless Transistors by Gate and Dielectric Engineering,” 2019 Devices for Integrated Circuit (DevIC), Kalyani, India, 2019, pp. 484-488.
    doi: 10.1109/DEVIC.2019.8783415
11. S. K. Reddy and G. Saini, “Design of Carry Select Adder with Online Testability Using Reversible Gates,” 2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT), Bangalore, India, 2019, pp. 486-490, doi: 10.1109/RTEICT46194.2019.9016873.
12. Beniwal and G. Saini, “L-shaped Tunnelling Field Effect Transistor with hetero-gate dielectric and hetero dielectric box,” 2019 3rd International Conference on Trends in Electronics and Informatics (ICOEI), Tirunelveli, India, 2019, pp. 815-818, doi: 10.1109/ICOEI.2019.8862520.
13. Saini and G. Saini, “Spacer Engineered Junction-Less Transistor: A Device Circuit Co-Design Study for Ultra-Low Power Applications,” 2018 Second International Conference on Intelligent Computing and Control Systems (ICICCS), Madurai, India, 2018, pp. 1445-1450.doi: 10.1109/ICCONS.2018.8662977
14. Bharti and G. Saini, “Sensitivity Analysis of Junctionless FinFET for Analog Applications,” 2018 Second International Conference on Intelligent Computing and Control Systems (ICICCS), Madurai, India, 2018, pp. 1288-1293.
    doi: 10.1109/ICCONS.2018.8662918
15. Singh, G. Saini and N. Singh, “An Efficient Model to Count Objects in Motion by Trading Off the Area Threshold,” 2018 International Conference on Inventive Research in Computing Applications (ICIRCA), Coimbatore, India, 2018, pp. 484-487.
    doi: 10.1109/ICIRCA.2018.8597418
16. Sai Charan and G. Saini, “Pedestrian Detection System with a Clear Approach on Raspberry Pi 3,” 2018 International Conference on Inventive Research in Computing Applications (ICIRCA), Coimbatore, India, 2018, pp. 601-604.
    doi: 10.1109/ICIRCA.2018.8597306
17. Rani and G. Saini, “Impact of Channel Engineering on Double Gate Junction Less Transistor for Improved Analog Performance,” 2018 International Conference on Emerging Trends and Innovations In Engineering And Technological Research (ICETIETR), Ernakulam, 2018, pp. 1-6.
18. Varsha Pathak, Gaurav Saini, “A Graded Channel Dual-Material Gate Junctionless MOSFET for Analog Applications,” Procedia Computer Science, Volume 125, 2018, Pages 825-831, ISSN 1877-0509, https://doi.org/10.1016/j.procs.2017.12.105.
19. Chahal and G. Saini, “Analog performance investigation of double gate junctionless transistor using spacer layer engineering,” 2017 8th International Conference on Computing, Communication and Networking Technologies (ICCCNT), Delhi, 2017, pp. 1-4.doi: 10.1109/ICCCNT.2017.8204086
20. Dwivedi and G. Saini, “Effect of random dopant fluctuation in nanoscale junctionless FinFET using low and high-k spacers,” 2017 8th International Conference on Computing, Communication and Networking Technologies (ICCCNT), Delhi, India, 2017, pp. 1-4.
    doi:10.1109/ICCCNT.2017.8204094
21. K. Pandey and G. Saini, “Study of self-heating effects on fully depleted SOI MOSFETs with BOX layer engineering,” 2017 International Conference on Trends in Electronics and Informatics (ICEI), Tirunelveli, 2017, pp. 962-965.
    doi: 10.1109/ICOEI.2017.8300850
22. Gehlawat and G. Saini, “Random dopant induced threshold voltage variation analysis of asymmetric spacer FinFETs,” 2017 International Conference on Trends in Electronics and Informatics (ICEI), Tirunelveli, 2017, pp. 953-956.
    doi: 10.1109/ICOEI.2017.8300848
23. Madhini and G. Saini, “Heterojunction tunnel FET with Heterodielectric BOX,” 2016 International Conference on Communication and Signal Processing (ICCSP), 2016, pp. 1743-1746, doi: 10.1109/ICCSP.2016.7754465.
24. Rohit and G. Saini, “A stable and power efficient SRAM cell,” 2015 International Conference on Computer, Communication and Control (IC4), 2015, pp. 1-5, doi: 10.1109/IC4.2015.7375605.
25. Jakhar and G. Saini, “Design of a novel regulated cascode current mirror,” 2015 International Conference on Computer, Communication and Control (IC4), 2015, pp. 1-4, doi: 10.1109/IC4.2015.7375599.
26. N. Bhargav, A. Suresh and G. Saini, “Stacked keeper with body bias: A new approach to reduce leakage power for low power VLSI design,” 2014 IEEE International Conference on Advanced Communications, Control and Computing Technologies, 2014, pp. 445-450, doi: 10.1109/ICACCCT.2014.7019482.
27. Dillep and G. Saini, “Enhanced cascode node impedance to the improved recyclic folded cascode OTA,” 2014 IEEE International Conference on Advanced Communications, Control and Computing Technologies, 2014, pp. 451-455, doi: 10.1109/ICACCCT.2014.7019483.
28. Saini, A. K. Rana, P. K. Pal and S. Jadav, “Leakage behavior of underlap FinFET structure: A simulation study,” 2010 International Conference on Computer and Communication Technology (ICCCT), 2010, pp. 302-305, doi: 10.1109/ICCCT.2010.5640528.
29. K. Pal, R. S. Rathore, A. K. Rana and G. Saini, “New low-power techniques: Leakage Feedback with Stack & Sleep Stack with Keeper,” 2010 International Conference on Computer and Communication Technology (ICCCT), 2010, pp. 296-301, doi: 10.1109/ICCCT.2010.5640514.
30. Jadav, G. Khanna, A. Kumar and G. Saini, “Low power high throughput current mode signalling technique for global VLSI interconnect,” 2010 International Conference on Computer and Communication Technology (ICCCT), 2010, pp. 290-295, doi: 10.1109/ICCCT.2010.5640513.

Book Chapters:

1. Gaurav Saini, Trailokya Nath Sasamal, Fully Depleted Planar Bi-layer Junctionless, CRC Press, Pages 231-238, 2023. eBook ISBN9781003361633
2. Trailokya Nath Sasamal, Hari Mohan Gaur, Vineet Jaiswal, Gaurav Saini, Ashutosh Kumar Singh, High-Speed Comparator and Parity Generator Towards Simplified Clocking Circuit in QCA Technology, CRC Press, Pages 99-114, 2023. eBook ISBN9781003361633
3. Nisha Yadav, Sunil Jadav, Gaurav Saini, Simulation and Analysis of Gate Stack DG MOSFET with Application of High-k Dielectric Using Visual TCAD, in High-k Materials in Multi-Gate FET Device, CRC Press, Pages 26, 2021. ISBN9781003121589
4. Gaurav Saini, Trailokya Nath Sasamal, Asymmetric Junctionless Transistor: A SRAM Performance Study, in High-k Materials in Multi-Gate FET Device, CRC Press, Pages 10, 2021. ISBN9781003121589
5. Abhinav Rajyan, Gaurav Saini, Dual Pocket Step Channel TFET for Improved Low-Power Performance, Nano-FET Devices: Miniaturization, Simulation, and Applications (Part 1), Pages 225-252, Bentham Science Publishers, Publication date 2025/9/26 (September 2025)
6. Nisha Yadav, Sunil Jadav, Gaurav Saini, The Tunnel FET Fundamentals, Calibration, and Simulation, in Nanoelectronics: Fundamentals, Advances, and Applications, Wiley ISBN:9781394275199 (September 2025)

 

 

 

Email:    gauravsaini@nitkkr.ac.in
Phone No:    01744-233141, 8950461132